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21 lines
665 B
Makefile
21 lines
665 B
Makefile
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#This variable is used to specify all the object file
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#which will be loaded and compile as kernel module for
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#usage. And the compilation for obj file from .c file
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#is done automatically.
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obj-m += hello.o
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# M variable used here tells the "make" to look in
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# current path to build bootable kernel module from
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# .c files in specified current path.
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# modules: It is the target that is used to build the kernel
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# modules.
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# clean: It is used to clean the build targets, compile and
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# generated files which would be created.
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all:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
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clean:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
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