Makefile update

Makefile

@@ -1,3 +1,5 @@
+#make "rule" -f "makefile name"
+
 #############GUIDE LIST##########################################
 #   G1.     CC:                                                 #
 #               Flag to mention the C compiler to used.         #
@@ -48,7 +50,8 @@
 #Flags
 # C program
 CC                              = gcc
-CFLAGS                          = -g
+INCDIRS                         = -I./include
+CFLAGS                          = -g $(INCDIRS)
 OUTPUT_OPTION                   = -MMD -MP -o $@
 SHARED_LIBRARY_EXTENSION        = so  
 SHARED_LIBRARY_FLAG             = -shared
@@ -88,6 +91,18 @@ ${EXE_NAME}: ${OBJS}
                 ${CC} ${OJBS} -o ${EXE_NAME}
 
 
+
+
+#regular expression where % is a wildcard
+%.o: %.c
+        $(CC) $(CFLAGS) -c $^ -o $@
+
+#OR
+
+%.o: %.c
+        $(CC) $(CFLAGS) -c -o $@ $^
+
+
 ##G12.
 #####SOURCE FILE DEPENDENT ON HEADER FILE################
 #   "src or obj file": "header file"                    #
@@ -131,8 +146,9 @@ ${LIB}.${SHARED_LIBRARY_EXTENSION}: ${OBJS}
 ##G14.
 ###MEANING OF $@ AND $^ SYMBOLS ON ABOVE RULE####################
 #       $@ -> Replacing itself with rule under which            #
-#             its written.                                      #
+#             its written.     (Left side of rule)              #
 #       $^ -> Replacing itself with dependencies of rule.       #
+#                              (Right side of rule)             #
 #################################################################